First in its track at the IIC IdeaThon and carried through to ElectroUtsav 2025 — a Verilog traffic controller on FPGA with a sub-10-nanosecond emergency override.
A smart adaptive traffic light controller, written in Verilog HDL and run on an FPGA. It took first place in its track at the IIC IdeaThon and was shortlisted through to ElectroUtsav 2025.
The controller adjusts green time to measured traffic density instead of running a fixed cycle, and it is built as a modular finite state machine so that every transition is deterministic and every timing figure is one you can reason about rather than measure and hope.
The emergency override is the part worth knowing about: it responds in under ten nanoseconds, because it is not software. There is no scheduler to wait for and no interrupt latency to argue about — the priority path is wired into the fabric, and that is precisely the reason to reach for hardware rather than a microcontroller and a loop.
It is also the clearest lesson on this timeline about choosing a substrate. The same behaviour in firmware would have been easier to write, impossible to guarantee, and wrong for the one requirement that actually mattered.
Divyakush Punjabi