Adaptive Traffic Light Controller — Verilog FPGA Design

Real-time traffic controller that adjusts signal timing to measured vehicle throughput, written in Verilog and synthesised to FPGA.

A real-time adaptive traffic management system implemented on FPGA in Verilog, optimising vehicle throughput by adjusting signal timing dynamically rather than running a fixed cycle.

Language: Verilog
Target: FPGA
Level: RTL

What it had to solve

A fixed-cycle traffic light is optimal for exactly one traffic pattern and wrong the rest of the day — it holds an empty approach on green while a queue builds on the other. Adapting means measuring demand and changing timing while the junction is running, and doing it with hard timing guarantees, which is a poor fit for software on a general-purpose processor and a natural one for hardware.

The decisions that shaped it

A state machine in hardware, not software

The controller is written in Verilog at register-transfer level and synthesised to an FPGA. Signal control is a hard-real-time problem where a missed deadline is a safety property, not a dropped frame — expressing it as synchronous logic gives timing that is guaranteed by the clock rather than by a scheduler.

Timing driven by measured throughput

Phase durations respond to measured vehicle throughput instead of a preset cycle, so green time follows demand. That is the entire difference between this and a conventional fixed-plan controller.

Parallel by construction

On an FPGA the approaches are evaluated concurrently rather than in a loop, so adding another one costs area rather than latency — the response time of the junction does not degrade as it grows.

RTL through to synthesis

The design was carried from RTL description through to synthesis on the target device, which is where a hardware design stops being a simulation and starts having a real critical path.